منابع مشابه
Deterministic BIST for RNS Adders
Modulo 2 ÿ 1 adders as fast as n-bit 2’s complement adders have been recently proposed in the open literature. This makes a Residue Number System (RNS) adder with channels based on the moduli 2, 2 ÿ 1, and any other of the form 2 ÿ 1, with k < n, faster than RNS adders based on other moduli. In this paper, we formally derive a parametric, with respect to the adder size, test set, for parallel t...
متن کاملEfficient BIST schemes for RNS datapaths
It has recently been shown that accumulators can be used elfciently for test pattem generation as well as for test response compaction. In this paper we present a BIST scheme for accumulators where the accumulator is simultaneously used as a test pattern generator and a response compactor during its own testing. We also show that the proposed BlST scheme is especially suitable for accumulator, ...
متن کاملAccumulator based deterministic BIST
Most built-in self test (BIST) solutions require specialized test pattern generation hardware which may introduce significant area overhead and performance degradation. Recently, some authors proposed test pattern generation on chip by means of functional units also used in system mode like adders or multipliers. These schemes generate pseudo-random or pseudo-exhaustive patterns for serial or p...
متن کاملImproving System Performance by Using Prefix Adders in Rns
over the past few decades, the intense growth of portable communication devices leads to stringent need of efficient system performance. The system performance is upgraded by reducing the computation time. The Residue Number System performs the computations fast and makes use of the power and energy efficiently. In this paper, the modified prefix adders are proposed to perform the fast modulo c...
متن کاملDeterministic BIST with multiple scan chains
A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage. The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.
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ژورنال
عنوان ژورنال: IEEE Transactions on Computers
سال: 2003
ISSN: 0018-9340
DOI: 10.1109/tc.2003.1214338